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description the CXP88732/88740/88748 is a cmos 8-bit microcomputer which consists of a/d converter, serial interface, timer/counter, time base timer, high precision timing pattern generation circuits, pwm output, viss/ vass circuit, 32khz timer/counter, remote control receiving circuit, vsync separator and the measurement circuit which measure signals of capstan fg amplifier and drum fg/pg amplifier and other servo systems, as well as basic configurations like 8-bit cpu, rom, ram and i/o port. they are integrated into a single chip. also, CXP88732/88740/88748 provides sleep/stop function which enables to lower power consumption. features a wide instruction set (213 instructions) which cover various types of data ?16-bit arithmetic/multiplication and division/boolean bit operation instructions minimum instruction cycle 250ns at 16mhz operation 122s at 32khz operation incorporated rom capacity 32k bytes (CXP88732) 40k bytes (cxp88740) 48k bytes (cxp88748) incorporated ram capacity 1344 bytes (including ppg ram) peripheral function ?a/d converter 8 bits, 14 channels, successive approximation system (conversion time of 20s/16mhz) ?serial interface incorporated 8-bit, 8-stage fifo for data (auto transfer for 1 to 8 bytes), 1 channel 8-bit clock sync type, 1 channel ?timer 8-bit timer/counter, 2 channels 19-bit time base timer 32khz timer/counter ?high precision timing pattern generation ppg 19 pins 32-stage programmable circuit rtg 5 pins, 1 channel 5-bit, 8-satge fifo (recctl control), 1channel ?pwm/da gate output 12 bits, 2 channels (repetitive frequency 62.5khz/16mhz) da gate pulse output, 13 bits, 2 channels ?analog signal input circuit capstan fg amplifier circuit drum fg amplifier circuit drum pg amplifier circuit pbctl amplifier circuit ?ctl write/rewrite circuit recording current control circuit ?servo input control capstan fg, drum fg/pg, ctl input ?vsync separator ?frc capture unit incorporated 26-bit and 8-stage fifo ?pwm output 14-bit, 1 channel ?viss/vass circuit pulse duty auto detection circuit ?32khz timer/event counter 32khz oscillation circuit, ultra-low speed instruction mode ?remote control reception circuit 8-bit pulse measurement counter, 6-stage fifo ?tri-state output ppg 1 pin, output 8 pins ?pseudo hsync output function ?high speed head switching circuit interruption 20 factors, 15 vectors, multi-interruption possible standby mode sleep/stop package 100-pin plastic qfp piggyback/evaluation chip cxp88800 100-pin ceramic qfp ?1 CXP88732/88740/88748 100 pin qfp (plastic) e96109-st cmos 8-bit single chip microcomputer sony reserves the right to change products and specifications without prior notice. this information does not convey any licens e by any implication or otherwise under any patents or other right. application circuits shown, if any, are typical examples illustr ating the operation of the devices. sony cannot assume responsibility for any problems arising out of the use of these circuits. structure silicon gate cmos ic
? 2 CXP88732/88740/88748 s o 1 a p a 0 t o p a 7 p b 0 t o p b 7 p c 0 t o p c 7 p d 0 t o p d 7 p e 0 , 1 , 6 , 7 p e 2 t o p e 5 p f 0 t o p f 3 p f 4 t o p f 7 p g 0 , 1 p i 0 t o p i 7 v s s v d d m p r s t x t a l e x t a l c l o c k g e n e r a t o r / s y s t e m c o n t r o l r a m 1 3 4 4 b y t e s s p c 7 0 0 c p u c o r e r o m 3 2 k / 4 0 k / 4 8 k b y t e s i n t e r r u p t c o n t r o l l e r 2 2 f i f o f r c c a p t u r e u n i t p r o g r a m a b l e p a t t e r n g e n e r a t o r r a m 2 a v s s a v r e f a v d d 2 a / d c o n v e r t e r s e r i a l i n t e r f a c e u n i t ( c h 0 ) f i f o 8 b i t t i m e r / c o u n t e r 0 v s y n c s e p a r a t o r 1 4 b i t p w m g e n e r a t o r 1 2 b i t p w m g e n e r a t o r c h 0 s e r v o i n p u t c o n t r o l g a i n c o n t r o l a m p 2 3 2 1 2 b i t p w m g e n e r a t o r c h 1 4 p w m 1 p w m 0 p w m r m c c t l a m p d p g d f g c f g e x i 1 e x i 0 s y n c e c s c k 1 s i 1 s c k 0 s o 0 s i 0 c s 0 a n 0 t o a n 1 3 r e a l t i m e p u l s e g e n e r a t o r i n t 2 i n t 0 1 4 8 p o r t a 8 p o r t b 8 p o r t c p o r t d 4 4 p o r t e 4 4 p o r t f 2 p o r t g 8 p o r t h 8 p o r t i p h 0 t o p h 7 t x t e x a i n t 1 / n m i p r e s c a l e r / t i m e b a s e t i m e r v i s s / v a s s r e m o c o n i n p u t f i f o s e r i a l i n t e r f a c e u n i t ( c h 1 ) c h 0 c h 1 p p o 0 t o p p o 1 8 r t o 3 t o r t o 7 8 b i t t i m e r / c o u n t e r 1 e c s e l e c t p s e u d o h s y n c g e n e r a t o r h g o 3 2 k h z t i m e r / c o u n t e r 2 d a a 1 d a a 0 t o p u l s e w i d t h c o u n t e r f i f o 8 1 9 5 c t l r / w c o n t r o l r e c c t l c t l c i n 2 a d j a m p v s s a m p v d d d d o 5 n m i block diagram
? 3 CXP88732/88740/88748 pin assignment (top view) p e 5 / e x i 1 p h 7 4 0 3 9 3 8 3 7 3 6 3 5 3 4 3 1 3 2 3 3 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 7 0 6 9 6 8 6 7 6 3 6 4 6 5 6 6 6 1 6 2 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 8 1 8 2 8 3 8 4 8 8 8 7 8 6 8 5 8 9 9 0 1 0 0 9 9 9 8 9 7 9 6 9 5 9 4 9 1 9 2 9 3 p e 6 / p w m 0 / d a a 0 p e 7 / p w m 1 / d a a 1 c f g d f g d p g v r e f o u t a m p v s s c t l s a m p i c t l f a m p o c t l a g c t l a m p ( + ) c t l a m p ( ) c t l c i n ( ) c t l c i n ( + ) r e c c t l ( + ) r e c c t l ( ) a m p v d d r e c c a p v d d a n 0 / a n o u t a n 1 a n 2 a n 3 p f 0 / a n 4 p f 1 / a n 5 a v d d a v r e f a v s s p f 2 / a n 6 p h 6 p h 5 p h 4 p h 3 p h 2 p h 1 p h 0 m p r s t v s s x t a l e x t a l p g 1 / a n 1 3 p g 0 / a n 1 2 p f 7 / a n 1 1 p f 6 / a n 1 0 p f 5 / a n 9 p f 4 / a n 8 p f 3 / a n 7 p b 5 / p p o 1 3 p b 4 / p p o 1 2 p b 3 / p p o 1 1 p b 2 / p p o 1 0 p b 1 / p p o 9 p b 0 / p p o 8 p c 7 / r t o 7 p c 6 / r t o 6 p c 5 / r t o 5 p c 4 / r t o 4 p c 3 / r t o 3 p c 2 / p p o 1 8 p c 1 / p p o 1 7 p c 0 / p p o 1 6 p i 7 p i 6 p i 5 p i 4 p i 3 p i 2 p i 1 / e c / i n t 2 p i 0 / i n t 0 / e n v - d e t p d 7 / s i 0 p d 6 / s o 0 p d 5 / s c k 0 p d 4 / c s 0 p d 3 / t o / d d o / a d j / s r v o p d 2 / p w m p d 1 / r m c p d 0 / i n t 1 / n m i p b 6 / p p o 1 4 p b 7 / p p o 1 5 p a 0 / p p o 0 / h g o p a 1 / p p o 1 p a 2 / p p o 2 p a 3 / p p o 3 p a 4 / p p o 4 p a 5 / p p o 5 p a 6 / p p o 6 p a 7 / p p o 7 n c v d d v s s t x t e x p e 0 / s c k 1 p e 1 / s o 1 p e 2 / s i 1 p e 3 / s y n c p e 4 / e x i 0 note) 1. nc (pin 90) is always connected to v dd . 2. v dd (pins 61 and 89) are both connected to v dd 3. vss (pins 41 and 88) are both connected to gnd. 4. mp (pin 39) must be connected to gnd.
? 4 CXP88732/88740/88748 pin description (port a) 8-bit output port. data is gated with ppo contents by or-gate and they are output. (8 pins) (port b) 8-bit output port. data is gated with ppo contents by or-gate and they are output. tri-state control is possible. (8 pins) (port c) 8-bit i/o port. i/o can be set in a unit of single bits. data is gated with ppo or rt contents by or-gate and they are output. (8 pins) (port d) 8-bit i/o port. i/o can be set in a unit of single bits. (8 pins) (port e) 8-bit port. bits 2, 3, 4 and 5 are for inputs; bits 0, 1, 6 and 7 are for outputs. (8 pins) programmable pattern generator (ppg) output. functions as high precision real- time pulse output port. (19 pins) pa0 can be tri-state controlled with ppg. pseudo hsync output pin. real-time pulse generator (rtg) output. functions as high precision real-time pulse output port. (5 pins) input pin to request external interruption and non-maskable interruption. remote control receiving circuit input pin. 14-bit pwm output pin. timer/counter, ctl duty detector, 32khz oscillation adjustment and servo amplifier output pin. serial chip select (ch0) input pin. serial clock (ch0) i/o pin. serial data (ch0) output pin. serial data (ch0) input pin. serial clock (ch1) i/o pin serial data (ch1) output pin serial data (ch1) input pin composite sync signal input pin. external input pin for frc capture unit. (2 pins) symbol i/o description pa0/ppo0 /hgo pa1/ppo1 to pa7/ppo7 pb0/ppo8 to pb7/ppo15 pc0/ppo16 to pc2/ppo18 pc3/rto3 to pc7/rto7 pd0/int1/ nmi pd1/rmc pd2/pwm pd3 /to ddo/adj srvo pd4/cs0 pd5/sck0 pd6/so0 pd7/si0 pe0/sck1 pe1/so1 pe2/si1 pe3/sync pe4/exi0 pe5/exi1 pe6/pwm0/ daa0 pe7/pwm1/ daa1 pwm output pin. (2 pins) da gate pulse output pin. (2 pins) output/real-time output/output output/ real-time output output/ real-time output i/o/ real-time output i/o/ real-time output i/o/input/input i/o/input i/o/output i/o/output/output/ output/output i/o/input i/o/i/o i/o/output i/o/input output/i/o output/output input/input input/input input/input input/input output/output output/output
? 5 CXP88732/88740/88748 an0/anout an1 to an3 pf0/an4 to pf3/an7 pf4/an8 to pf7/an11 pg0/an12 pg1/an13 ph0 to ph7 pi0/int0/ env-det pi1/ec/ int2 pi2 to pi7 cfg dfg dpg recctl (+) recctl (? ctlcin (+) ctlcin (? ctlamp (+) ctlamp (? ctlfampo ctlsampi reccap vrefout ctlag ampv ss ampv dd input/output input input/input output/input input/input output i/o/input i/o/input/input i/o input input input i/o output input output input i/o output output description i/o description (port f) lower 4 bits are for inputs; upper 4 bits are for outputs. lower 4 bits are standby release input pins. (8 pins) (port g) 2-bit input port. (2 pins) analog circuit internal waveform output pin. (port h) 8-bit output port; n-ch open drain output of medium drive voltage (12v) and large current (12ma). (8 pins) (port i) 8-bit i/o port. i/o can be set in a unit of single bits. function as standby release input can be set in a unit of single bits. (8 pins) input pin to request external interruption. active when falling edge. external event input pin for timer/counter. trigger pulse input pin for head switching. input pin to request external interruption. active when falling edge. capstan fg input pin. drum fg input pin. drum pg input pin. recctl signal output pin. (2 pins) connected to recctl (+) and recctl (? with the internal switch for playback. (2 pins) input pbctl signal with capacitor coupled. (2 pins) pbctl signal 1st amplifier output. pbctl signal 2nd amplifier input. capacitor connecting pin for the slope setting of the ctl writing trapezoidal wave. capacitor connecting pin for the vref level smoothing of dpg, dfg and cfg. capacitor connecting pin for the ctl and agnd smoothing. analog signal input circuit gnd pin. analog signal input circuit power supply pin. pbctl signal input pin. (2 pins) analog input pin for a/d converter. (14 pins)
? 6 CXP88732/88740/88748 extal xtal tex tx rst nc mp av dd av ref av ss v dd v ss input output input output input input input symbol i/o description connecting pin of crystal oscillator for system clock. when supplying the external clock, input it to extal pin and input the opposite phase clock to xtal pin. connecting pin of crystal oscillator for 32khz timer clock. when used as event counter, input to tex pin and leave tx pin open. (in this time, feedback resistor is not removed.) system reset pin; low level active. nc pin. connect this pin to v dd for normal operation. test mode input pin. always connect to gnd. positive power supply pin for a/d converter. reference voltage input pin for a/d converter. gnd pin for a/d converter. positive power supply pin. gnd pin. connect both vss pins to gnd.
? 7 CXP88732/88740/88748 when reset pin circuit format input/output circuit formats for pins a a a a a a a a a a a a p p o d a t a d a t a b u s o u t p u t b e c o m e s a c t i v e f r o m h i g h i m p e d a n c e b y d a t a w r i t i n g t o p o r t . p o r t a d a t a r d ( p o r t a ) port a hi-z hi-z hi-z pa1/ppo1 pa2/ppo2 to pa7/ppo7 port b 6 pins 8 pins hi-z pb0/ppo8 to pb7/ppo15 port a d a t a b u s r d ( p o r t a ) a a a a a a a a p a 0 a a a a d a t a b u s r d ( p o r t a ) a a a a a a p a 1 a a a a p p o 1 p p g c o n t r o l s t a t u s r e g i s t e r b i t 0 t r i - s t a t e c o n t r o l s e l e c t i o n p p o 1 a a a a a a a a m p x a a a a a a a a a m p x p p o 0 h o u t h o u t e h s e l o u t p u t b e c o m e s a c t i v e f r o m h i g h i m p e d a n c e b y d a t a w r i t i n g t o p o r t . o u t p u t b e c o m e s a c t i v e f r o m h i g h i m p e d a n c e b y d a t a w r i t i n g t o p o r t . a a a a a a a a d a t a b u s p o r t b d a t a r d ( p o r t b ) a a a a a a a a p o r t b t r i - s t a t e c o n t r o l r t o d a t a pa0/ppo0/ hgo 1 pin 1 pin
? 8 CXP88732/88740/88748 when reset pin circuit format p p o , r t o d a t a d a t a b u s r d ( p o r t c ) a a a a a a a a a a a a p o r t c d i r e c t i o n a a a a a a a a p o r t c d a t a i p a a a a i n p u t p r o t e c t i o n c i r c u i t r d ( p o r t c d i r e c t i o n ) port d 8 pins hi-z hi-z pc0/ppo16 to pc2/ppo18 pc3/rto3 to pc7/rto7 pd0/int1/ nmi pd1/rmc pd4/cs0 pd7/si0 port d 4 pins 2 pins hi-z pd2/pwm pd3/to/ ddo/adj/ srvo port c a a a a a a a a a a m p x a a a a a a p o r t d d a t a a a a a i p d a t a b u s r d ( p o r t d ) a a a a a a p o r t d d i r e c t i o n a a a a a a a a p o r t d f u n c t i o n s e l e c t p d 2 . . . 1 4 - b i t p w m p d 3 . . . t i m e r / c o u n t e r , c t l d u t y d e t e c t i o n c i r c u i t , 3 2 k h z t i m e r , a m p l i f i e r c i r c u i t a a a a a a a a a a a a p o r t d d a t a a a i p d a t a b u s r d ( p o r t d ) a a a a a a a a p o r t d d i r e c t i o n p d 1 . . . r e m o t e c o n t r o l c i r c u i t p d 0 . . . i n t e r r u p t i o n c i r c u i t p d 4 , 7 . . . s e r i a l c h 0 s c h m i t t i n p u t
? 9 CXP88732/88740/88748 when reset pin circuit format d a t a b u s r d ( p o r t e ) a a a a a a a a a a a a a a a a a a a a s i 0 c h 1 h i - z c o n t r o l m p x a a a a a a a a p o r t e d a t a p o r t e f u n c t i o n s e l e c t d a t a b u s r d ( p o r t e ) a a a a a a a a a a a a a a a a a a a a s i 0 c h 1 h i - z c o n t r o l m p x a a a a a a a a p o r t e d a t a p o r t / s c k o u t p u t s e l e c t a a i p s i 0 c h 1 a a a a a a a a a a a a a a a a m p x a a a p o r t d d a t a a i p d a t a b u s r d ( p o r t d ) a a a p o r t d d i r e c t i o n a a a a a a a a p o r t d f u n c t i o n s e l e c t a a a a a a m p x s i 0 c h 0 s i 0 c h 0 n o t e ) p d 5 i s s c h m i t t i n p u t p d 6 i s i n v e r t e r i n p u t port e 2 pins hi-z hi-z hi-z pd5/sck0 pd6/so0 pe0/sck1 port e port e 1 pin 1 pin 4 pins hi-z pe1/so1 pe2/si1 pe3/sync pe4/exi0 pe5/exi1 port d a a a a i p r d ( p o r t e ) d a t a b u s s c h m i t t i n p u t p e 2 . . . s i 0 c h 1 p e 3 p e 4 s e r v o i n p u t p e 5 note) for pe3/sync, cmos schmitt input or ttl schmitt input can be selected with the mask oprion.
? 10 CXP88732/88740/88748 d a t a b u s r d ( p o r t e ) a a a a a a a a a a a a a a a a a a a a d a g a t e o u t p u t o r p w m o u t p u t h i - z c o n t r o l m p x a a a a a a a a p o r t e d a t a p o r t / d a / p w m s e l e c t 4 pins 2 pins hi-z hi-z hi-z hi-z when reset pe6/pwm0/ daa0 pe7/pwm1/ daa1 pf4/an8 to pf7/an11 an0/anout 1 pin 3 pin an1 to an3 4 pins high level pfo/an4 to pf3/an7 port e pin circuit format a a a a a a a a p o r t f d a t a a a a a i p d a t a b u s r d ( p o r t f ) a a a a a a a a a a p o r t / a d s e l e c t a / d c o n v e r t e r i n p u t m u l t i p l e x e r f r o m a m p l i f i e r c i r c u i t a a a a a a a a i p i n p u t m u l t i p l e x e r a / d c o n v e r t e r a a a a a a a a a n a l o g o u t p u t c o n t r o l a a a a a a a a i p i n p u t m u l t i p l e x e r a / d c o n v e r t e r port e port f r d ( p o r t f ) d a t a b u s a a a a a a a a i p i n p u t m u l t i p l e x e r a / d c o n v e r t e r port f
? 11 CXP88732/88740/88748 when reset pin circuit format r d ( p o r t g ) d a t a b u s a a a a a a a a i p i n p u t m u l t i p l e x e r a / d c o n v e r t e r a a a a a a a a a a a a p o r t i d a t a a a a a i p d a t a b u s r d ( p o r t i ) a a a a a a a a p o r t i d i r e c t i o n r d ( p o r t i d i r e c t i o n ) s t a n d b y r e l e a s e d a t a b u s a a a a e d g e d e t e c t i o n hi-z hi-z pg0/an12 to pg1/an13 2 pins 8 pins 6 pins hi-z hi-z ph0 to ph7 d a t a b u s r d ( p o r t h ) a a a a a a p o r t h d a t a a a a a l a r g e c u r r e n t 1 2 m a m e d i u m d r i v e v o l t a g e 1 2 v port h pi0/int0/ evn-det to pi1/ec/int2 a a a a a a a a a a a a p o r t i d a t a a a a a i p d a t a b u s r d ( p o r t i ) a a a a a a a a p o r t i d i r e c t i o n r d ( p o r t i d i r e c t i o n ) s t a n d b y r e l e a s e i n t e r r u p t i o n c i r c u i t d a t a b u s a a a a e d g e d e t e c t i o n 2 pins pi2 to pi7 port i port g port i
? 12 CXP88732/88740/88748 when reset pin circuit format a a a a a a a a a a i n p u t p i n c h a r g e c o n t r o l a a a a a a i p a a a a i p a a a a c t l a m p ( ) c t l a m p ( + ) a a a a a a c t l f a m p o a c t l a g 2 pins 3 pins 1/2ampv dd 1/2ampv dd 1/2ampv dd ctlamp (+) ctlamp ( ) ctlfampo ctlag vrefout ctlsampi 1 pin 3 pins 1/2ampv dd cfg dfg dpg a a a a i p a a a a l p f c i r c u i t a a a a v r e f o u t a a a a a a a a a a i n p u t p i n c h a r g e c o n t r o l a a a a a m p v d d a a a a i p a m p v s s v r e f o u t . . . c t l a g . . . . . . . . c f g , d f g , d p g a m p l i f i e r s c t l a m p l i f i e r a a a a i p a a a a l p f c i r c u i t a a a a c t l a g a a a a a a a a a a i n p u t p i n c h a r g e c o n t r o l
? 13 CXP88732/88740/88748 a a a i p a m p v s s r t g c o n t r o l p e r m i s s i o n r t o 3 f r o m r e c c t l ( ) p i n a a a a a a a a i p c t l c i n ( + ) p i n a a a a r e c o r d i n g c u r r e n t c o n t r o l c i r c u i t a m p v s s w r i t e c u r r e n t s e l e c t r t g c o n t r o l p e r m i s s i o n r t o 6 r t o 7 r t o 3 a m p v d d 1 pin 1 pin 1 pin hi-z hi-z hi-z low level when reset recctl (+) ctlcin ( ) reccap recctl ( ) 1 pin 1 pin hi-z ctlcin (+) pin circuit format a a a i p a m p v s s r t g c o n t r o l p e r m i s s i o n r t o 3 f r o m r e c c t l ( + ) p i n a a r t g c o n t r o l p e r m i s s i o n r t o 5 r e c o r d i n g c u r r e n t c o n t r o l c i r c u i t a a i p a a a a c t l c i n ( e ) p i n a a a a r e c o r d i n g c u r r e n t c o n t r o l c i r c u i t a m p v s s w r i t e c u r r e n t s e l e c t r t g c o n t r o l p e r m i s s i o n r t o 7 r t o 6 r t o 3 a m p v d d a a a a i p
? 14 CXP88732/88740/88748 2 pins oscillation extal xtal a a a a a a a a i p a a a a e x t a l x t a l s h o w s t h e c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d a n d x t a l b e c o m e s h i g h l e v e l d u r i n g s t o p . 2 pins oscillation tex tx a a a a a a a a i p a a a a t e x t x s h o w s t h e c i r c u i t c o m p o s i t i o n d u r i n g o s c i l l a t i o n . f e e d b a c k r e s i s t o r i s r e m o v e d d u r i n g 3 2 k h z o s c i l l a t i o n c i r c u i t s t o p b y s o f t w a r e . a t t h i s t i m e , t e x p i n o u t p u t s l o w l e v e l a n d t x p i n o u t p u t s h i g h l e v e l . 3 2 k h z t i m e r / c o u n t e r 1 pin low level rst a a a a a a i p s c h m i t t i n p u t p u l l u p r e s i s t o r o p m a s k o p t i o n when reset pin circuit format
? 15 CXP88732/88740/88748 * 1) av dd and v dd must not exceed +0.3v. * 2) ampv dd and v dd must not exceed +0.3v. * 3) v in and v out must not exceed v dd +0.3v. * 4) the large current output port is port h (ph). note) usage exceeding absolute maximum ratings may permanently impair the lsi. normal operation should better take place under the recommended operating conditions. exceeding those conditions may adversely affect the reliability of the lsi. supply voltage input voltage output voltage medium drive output voltage high level output current high level total output current low level output current low level total output current operating temperature storage temperature allowable power dissipation v dd av dd av ss ampv dd ampv ss v in v out v outp i oh i oh i ol i olc i ol topr tstg p d ?.3 to +7.0 avss to +7.0 * 1 ?.3 to +0.3 ampv ss to +7.0 * 2 ?.3 to +0.3 ?.3 to +7.0 * 3 ?.3 to +7.0 * 3 ?.3 to +15.0 ? ?0 15 20 130 ?0 to +75 ?5 to +150 600 v v v v v v v v ma ma ma ma ma c c mw port h total of output pins other than large current output ports (value per pin) large current output port * 4 (value per pin) total of output pins qfp package type item symbol rating unit remarks absolute maximum ratings (vss = 0v reference)
? 16 CXP88732/88740/88748 analog power supply high level input voltage low level input voltage operating temperature supply voltage 5.5 5.5 5.5 5.5 5.5 5.5 v dd v dd v dd v dd + 0.3 0.3v dd 0.2v dd 0.8 0.4 +75 v v v v v v v v v v c v item symbol min. max. unit remarks 4.5 3.5 2.7 2.5 4.5 4.5 0.7v dd 0.8v dd 2.2 v dd ?0.4 0 0 0 ?.3 ?0 av dd ampv dd v ih v ihs v ihts v ihex v il v ils v ilts v ilex topr guaranteed operation range for 1/2 and 1/4 frequency dividing clock guaranteed operation range for 1/16 frequency dividing clock or during sleep mode guaranteed operation range by tex clock guaranteed data hold operation range during stop * 1 * 2 * 3 cmos schmitt input * 4 ttl schmitt input * 5 extal pin * 6 tex pin * 7 * 3 cmos schmitt input * 4 ttl schmitt input * 5 extal pin * 6 tex pin * 7 v dd * 1) av dd and v dd should be set to the same voltage. * 2) ampv dd and v dd should be set to the same voltage. * 3) normal input port (each pin of pc, pd2, pd3, pd6, pf0 to pf3, pg and pi2 to pi7), mp pin * 4) each pin of rst, pd0/int1/nmi, pd1/rmc, pd4/cs0, pd5/sck0, pd7/si0, pe0/sck1, pe2/si1, pe3/sync, pe4/exi0, pe5/exi1, pi0/int0, pi1/ec/int2 (for pe3/sync, when cmos schmitt input is selected with mask option.) * 5) pe3/sync (when ttl schmitt input is selected with mask option.) * 6) specifies only during external clock input. * 7) specifies only during external event input. recommended operating conditions (vss = 0v)
? 17 CXP88732/88740/88748 v dd = 4.5v, i oh = ?.5ma v dd = 4.5v, i oh = ?.2ma v dd = 4.5v, i ol = 1.8ma v dd = 4.5v, i ol = 3.6ma v dd = 4.5v, i ol = 12.0ma v dd = 5.5v, v ih = 5.5v v dd = 5.5v, v il = 0.4v v dd = 5.5v, v ih = 5.5v high level output voltage 4.0 3.5 0.5 ?.5 0.1 ?.1 ?.5 v v v v v a a a a a a a ph extal tex rst * 1 item symbol pins conditions min. clock 1mhz 0v other than the measured pins v dd, v ss i dd1 i iz i loh i dds1 i dd2 i dds2 i dds3 c in v oh v ol i ihe i ile i iht i ilt i ilr low level output voltage input current typ. 0.4 0.6 1.5 40 ?0 10 ?0 ?00 10 50 max. unit dc characteristics (v dd = 4.5 to 5.5v) electrical characteristics (ta = ?0 to +75 c, vss = 0v reference) * 1) rst pin specifies the input current when the pull-up resistor is selected, and specifies leakage current when no resistor is selected. * 2) when entire output pins are open. * 3) when setting upper 2 bits (cpu clock selection) of clock control register (clc: 00fe h ) to "00" and operating in high speed mode (1/2 frequency dividing clock). v dd = 5.5v * 3 sleep mode v dd = 5.5v v dd = 5v 0.5v supply current * 2 input capacity v dd = 5.5v, v il = 0.4v v dd = 5.5v, v i = 0, 5.5v v dd = 5.5v v oh = 12v 16mhz crystal oscillation (c 1 = c 2 = 15pf) stop mode (extal and tex pins oscillation stop) i/o leakage current open drain output leakage current (n-ch tr off state) pa to pg, pi, mp, an0 to an3, rst * 1 ph 35 2.0 50 9 10 45 8 100 35 10 20 ma ma a a a pf v dd = 3.3v sleep mode v dd = 3v 0.3v 32khz crystal oscillation (c 1 = c 2 = 47pf) pa to pd, pe0 to pe1, pe6 to pe7, pf4 to pf7, p h (v ol only) pi pc, pd, pe0, pe2 to pe5 pf, pg, pi, recctl (+), recctl (?, ctlamp (+), ctlamp (?, ctlsampi, cfg, dfg, dpg, extal, tex
? 18 CXP88732/88740/88748 t e x e c t e h t e l t e f t e r 0 . 2 v d d 0 . 8 v d d t t h t t l t t f t t r fig. 3. event count clock timing * 1) t sys indicates three values according to the contents of the clock control register (clc; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") e x t a l x t a l t x h t x l t c f t c r 0 . 4 v v d d 0 . 4 v 1 / f c a a a a a a a a a a a a a a a e x t e r n a l c l o c k e x t a l x t a l 7 4 h c 0 4 a a a a a a a a a a a a c r y s t a l o s c i l l a t i o n c e r a m i c o s c i l l a t i o n e x t a l x t a l c 1 c 2 a a a a a a a a a a a a a a a 3 2 k h z c l o c k a p p l i e d c o n d i t i o n c r y s t a l o s c i l l a t i o n t e x t x c 1 c 2 ac characteristics (1) clock timing system clock frequency system clock input pulse width system clock input rise and fall times event count clock input pulse width event count clock input rise and fall times system clock frequency event count clock input pulse width event count clock input rise and fall times f c t xl , t xh t cr , t cf t eh , t el t er , t ef f c t tl , t th t tr , t tf xtal extal xtal extal xtal extal ec ec tex tx tex tex mhz ns ns ns ms khz s ms item symbol pin condition unit fig. 1, fig. 2 fig. 1, fig. 2 external clock drive fig. 1, fig. 2 external clock drive fig. 3 fig. 3 v dd = 2.7 to 5.5v fig. 2 (32khz clock applied condition) fig. 3 fig. 3 typ. 32.768 min. 1 28 t sys + 200 * 1 10 max. 16 200 20 20 (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) fig. 1. clock timing fig. 2. clock applied condition
? 19 CXP88732/88740/88748 input mode output mode input mode output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode sck0 input mode sck0 output mode chip select transfer mode (sck0 = output mode) chip select transfer mode (sck0 = output mode) chip select transfer mode chip select transfer mode chip select transfer mode note 1) t sys indicates three values according to the contents of the clock control register (clc; 00fe h ) upper 2 bits (cpu clock selection). t sys [ns] = 2000/fc (upper 2 bits = "00"), 4000/fc (upper 2 bits = "01"), 16000/fc (upper 2 bits = "11") note 2) the load of sck0 output mode and so0 output delay time is 50pf + 1ttl. (2) serial transfer (ch0) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item cs0 ? sck0 delay time cs0 - ? sck0 floating delay time cs0 ? so0 delay time cs0 - ? so0 floating delay time cs0 high level width sck0 cycle time sck0 high and low level widths si0 input set-up time (against sck0 - ) si0 input hold time (against sck0 - ) sck0 ? so0 delay time t dcsk t dcskf t dcso t dcsof t whcs t kcy t kh t kl t sik t ksi t kso sck0 sck0 so0 so0 cs0 sck0 sck0 si0 si0 so0 ns ns ns ns ns symbol pin min. t sys + 200 t sys + 200 t sys + 200 t sys + 200 t sys + 200 2 t sys + 200 16000/fc t sys + 100 8000/fc ?50 100 200 t sys + 200 100 ns ns ns ns ns ns ns ns ns ns t sys + 200 100 max. unit condition
? 20 CXP88732/88740/88748 fig. 4. serial transfer timing (ch0) c s 0 s c k 0 0 . 2 v d d 0 . 8 v d d t w h c s t d c s k t d c s k f 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d t k c y t k l t k h 0 . 8 v d d 0 . 2 v d d s i 0 t s i k t k s i i n p u t d a t a t d c s o t k s o t d c s o f o u t p u t d a t a 0 . 8 v d d 0 . 2 v d d s o 0
? 21 CXP88732/88740/88748 serial transfer (ch1) (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) item symbol pin min. max. unit condition sck1 cycle time sck1 high and low level widths si1 input set-up time (against sck1 - ) si1 input hold time (against sck1 - ) sck1 ? so1 delay time t kcy t kh t kl t sik t ksi t kso sck1 sck1 si1 si1 so1 input mode output mode input mode output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode sck1 input mode sck1 output mode 1000 16000/fc 400 8000/fc ?50 100 200 200 100 200 100 ns ns ns ns ns ns ns ns ns ns note) the load of sck1 output mode and so1 output delay time is 50pf + 1ttl. fig. 5. serial transfer timing (ch1) s c k 1 s i 1 s o 1 t k c y t k l t k h 0 . 2 v d d 0 . 8 v d d t s i k t k s i t k s o i n p u t d a t a o u t p u t d a t a 0 . 2 v d d 0 . 8 v d d 0 . 2 v d d 0 . 8 v d d
? 22 CXP88732/88740/88748 conversion time sampling time reference input voltage analog input voltage t conv t samp v ref v ian i ref ta = 25 c v dd = av dd = av ref = 5.0v v dd = avss = 0v operation mode sleep mode stop mode 32khz operation mode linearity error absolute error resolution av ref current av ref s s v v av dd av ref 1.0 ma 10 a 0.6 160/f adc * 1 12/f adc * 1 av dd ?0.5 0 item symbol pin condition min. typ. max. unit bits (3) a/d converter characteristics (ta = 20 to +75 c , v dd = av dd = 4.5 to 5.5v, av ref = 4.0 to av dd , vss = avss = 0v reference) 8 1 2 lsb lsb a n a l o g i n p u t l i n e a r i t y e r r o r v f t v z t 0 0 h 0 1 h f e h f f h d i g i t a l c o n v e r s i o n v a l u e fig. 6. definitions of a/d converter terms av ref an0 to an7 * 1) f adc indicates the below values due to the contents of bit 0 (adcck) of the adc operation clock selection register (msc: 01ff h ), bits 7 (pck1) and 6 (pck0) of the clock control register (address: 00fe h ). 00 ( f = f ex /2) 01 ( f = f ex /4) 11 ( f = f ex /16) f adc = fc/2 f adc = fc/4 f adc = fc/16 f adc = fc f adc = fc/2 f adc = fc/8 0 ( f /2 selection) 1 ( f selection) pck1, pck0 adcck
? 23 CXP88732/88740/88748 external interruption high and low level widths reset input low level width int0 int1 int2 nmi rst 1 32/fc s s item symbol pin condition min. max. unit t ih t il t rsl (4) interruption, reset input (ta = ?0 to +75 c, v dd = 4.5 to 5.5v, vss = 0v reference) 0 . 2 v d d 0 . 8 v d d t i h t i l i n t 0 i n t 1 i n t 2 n m i ( f a l l i n g e d g e ) fig. 7. interruption input timing t r s l 0 . 2 v d d r s t fig. 8. reset input timing
? 24 CXP88732/88740/88748 voltage gain * 1 offset voltage input resistance charge switch on resistance recctl and ctlcin connection switch on resistance ctlcin 0v fix switch on resistance item symbol pin conditions min. typ. max. unit db db db db mv k k (2) ctl 1st amplifier characteristics (ta = 20 to +75 c , v dd = ampv dd = 5.0v, vss = ampv ss = 0v, ctlag reference) gain = 16db recctl ( ) = 0v gain = 27db recctl ( ) = 0v gain = 42db recctl ( ) = 0v gain = 58db recctl ( ) = 0v ctlamp (+) and ctlamp ( ) = open charge switch off ctlamp (+) = +0.2v charge switch off ctlamp ( ) = +0.2v charge switch on ctlamp (+) = +0.5v charge switch on ctlamp ( ) = +0.5v during ctl read operation, ctlcin (+) ? recctl (+) = 0.2 v during ctl read operation, ctlcin ( ) ? recctl ( ) = 0.2v during ctl write operation, ctlcin (+) = ampv ss + 0.2v during ctl write operation, ctlcin ( ) = ampv ss + 0.2v a vctl1 v osctl 1 r inctl 1 r cctl 1 r read r write recctl (+) ctlfampo * 2 ctlamp (+) ctlamp (? ctlamp (+) ctlamp (? recctl (+) ctlcin (+) recctl (? ctlcin (? ctlcin (+) ctlcin (? 12.5 23.5 39.0 54.5 ?0 26.0 1.20 315 315 14.5 25.5 41.5 57.0 0 44.5 2.0 560 560 400 400 250 250 16.5 27.5 44.0 59.5 +40 1010 1010 770 770 310 310 * 1) when ctlcin (+), ctlamp (+) pins and ctlcin (?, ctlamp (? pins are ac coupled, and then the signal is input from recctl (+) pin. * 2) the result after measuring the ctlfampo output waveform or voltage gain. note) the gain increases by approximately 1.5db when the ac coupling capacitor (47 f) is connected to ctlamp (+) and ctlamp (? pins, and the signal is input from ctlamp (+) and ctlamp (? pins. reference level output voltage reference level output current v or i or vrefout ctlag vrefout ctlag item symbol pin conditions min. typ. max. unit v v ma ma ma ma analog circuit characteristics (1) amplifier circuit reference voltage characteristics (ta = 20 to + 75 c , v dd = ampv dd = 5.0v, vss = ampv ss = 0v reference) 2.6 2.55 vrefout = vrefout + 0.5v vrefout = vrefout ?0.5v ctlag = ctlag + 0.5v ctlag = ctlag ?0.5v 2.2 2.15 3.50 ?.30 2.80 ?.30 2.4 2.35 6.5 ?.85 5.5 ?.85
? 25 CXP88732/88740/88748 voltage gain * 1, * 2 lpf cut-off frequency * 1, * 2 offset voltage * 2 comparator level * 2 input resistance charge switch on resistance item symbol pin conditions min. typ. max. unit db db db db khz mv mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 - p k (3) ctl 2nd amplifier characteristics (ta = ?0 to +75 c , v dd = ampv dd = 5.0v, vss = ampv ss = 0v, ctlag reference) gain = 5db gain = 11db gain = 16db gain = 20db f dc ?3db ctlsampi = open comparator level = +100mv 0 -p comparator level = +250mv 0 -p comparator level = +400mv 0 -p comparator level = 100mv 0 -p comparator level = 250mv 0 -p comparator level = 400mv 0 -p charge switch off ctlsampi = +0.2v charge switch on ctlsampi = +0.5v a vctl2 f cctl v osctl2 v cctl r inctl2 r cctl2 ctlsampi 4.8 10.4 15.3 19.3 15.0 ?0 70.0 215 370 ?0.0 ?20 ?70 10.0 5.8 11.5 16.5 20.5 25.0 0 100 245 400 ?00 ?50 ?00 18.0 770 6.8 12.6 17.7 21.7 40.0 +50 130 275 430 ?30 ?80 ?30 1140 * 1) when the signal is input with the ac coupling capacitor (47 f) connected to ctlsampi pin. * 2) the result after measuring the output waveform of amplifier internal low-pass filter or voltage value. voltage gain * 1 input amplitude (peak value) input sensitivity input dead band item symbol pin conditions min. typ. max. unit db mv 0 -p mv 0 -p mv 0 -p (4) ctlamp characteristics (1st amplifier + 2nd amplifier) (ta = 20 to +75 c , v dd = ampv dd = 5.0v, vss = ampv ss = 0v reference) ctl 1st amplifier gain = 16db ctl 2nd amplifier gain = 20db recctl (? = 0v recctl (? = 0v ctl 1st amplifier gain = 58db ctl 2nd amplifier gain = 20db comparator level = +400mv 0 -p ?00mv 0 -p recctl (? = 0v a vctl v pkctl v sctl v nsctl recctl (+) 31.8 0.015 35.0 0.08 0.04 38.2 300 0.10 * 1) as for other combinations of the amplifier gains, ctl 1st amplifier and ctl 2nd amplifier are added respectively. note) the result when the signal is input from recctl (+) pin with ctl 1st amplifier + ctl 2nd amplifier after performing ac coupling of ctlcin (+), ctlamp (+) pins and ctlcin (?, ctlamp (? pins, and ctlfampo, ctlsampi pins.
? 26 CXP88732/88740/88748 voltage gain * 1 , * 2 lpf cut-off frequency * 1 , * 2 offset voltage * 2 comparator judgment level width * 2 input sensitivity * 1 input dead band * 1 input resistance charge switch on resistance digital output waveform duty * 1, * 3 input amplitude (peak value) * 1 item symbol pins conditions min. typ. max. unit db db db db khz mv mvp-p mvp-p mvp-p mvp-p mvp-p mvp-p k % v 0 -p (5) cfgamp characteristics (ta = ?0 to +75 c , v dd = ampv dd = 5.0v, vss = ampv dd = 0v, vrefout reference) gain = 0db gain = 20db gain = 34db gain = 38db f dc ?3db cfg = open comparator schimitt width = 320mv p-p comparator schimitt width = 160mv p-p gain = 38db comparator level = 320mv p-p gain = 38db comparator level = 160mv p-p gain = 38db comparator level = 320mv p-p gain = 38db comparator level = 160mv p-p charge switch off cfg = +0.2v charge switch on cfg = +0.5v cfg = sine wave with 50% duty a vcfg f ccfg v oscfg v ccfg v scfg v nscfg r incfg r ccfg d tycfg v pkcfg cfg ?.3 19.2 33.2 37.0 30.0 ?0 260 110 3.40 1.50 5.5 48.0 0.6 20.8 34.8 38.7 55.0 0 320 155 4.20 2.10 4.10 2.00 8.3 455 50.0 2.2 22.4 36.4 40.4 80.0 +50 360 200 5.00 2.40 710 52.0 2.4 * 1) when the signal is input with the ac coupling capacitor (47 f) connected to cfg pin. * 2) the result after measuring the output waveform of amplifier internal low-pass filter or voltage value. * 3) the result after measuring the digital signal waveform output from the amplifier circuit.
? 27 CXP88732/88740/88748 voltage gain * 1, * 2 lpf cut-off frequency * 1, * 2 offset voltage * 2 comparator judgment level width * 2 input sensitivity * 1 input dead band * 1 input resistance charge switch on resistance digital output waveform duty * 1, * 3 input amplitude (peak value) * 1 item symbol pins conditions min. typ. max. unit db db db db khz mv mvp-p mvp-p mvp-p mvp-p mvp-p mvp-p k % v 0 -p (6) dfgamp characteristics (ta = 20 to +75 c , v dd = ampv dd = 5.0v, vss = ampv ss = 0v, vrefout reference) gain = 0db gain = 20db gain = 34db gain = 38db f dc ?3db dfg = open comparator schmitt width = 320mv p-p comparator schmitt width = 160mv p-p gain = 38db comparator level = 320mv p-p gain = 38db comparator level = 160mv p-p gain = 38db comparator level = 320mv p-p gain = 38db comparator level = 160mv p-p charge switch off dfg = +0.2v charge switch on dfg = +0.5v cfg = sine wave of 50% duty a vdfg f cdfg v osdfg v cdfg v sdfg v nsdfg r indfg r cdfg d tydfg v pkdfg dfg ?.3 19.2 33.2 37.0 30.0 ?0 260 110 3.40 1.50 5.5 48.0 0.6 20.8 34.8 38.7 55.0 0 320 155 4.20 2.10 4.10 2.00 8.3 455 50.0 2.2 22.4 36.4 40.4 80.0 +50 360 200 5.00 2.40 710 52.0 2.4 * 1) when the signal is input with the ac coupling capacitor (47 f) connected to dfg pin. * 2) the result after measuring the output waveform of amplifier internal low-pass filter or voltage value. * 3) the result after measuring the digital signal waveform output from the amplifier circuit.
? 28 CXP88732/88740/88748 voltage gain * 1, * 2 lpf cut-off frequency * 1, * 2 offset voltage * 2 comparator level * 2 input sensitivity * 1 input dead band * 1 input resistance charge switch on resistance input amplitude (peak value) * 1 item symbol pins conditions min. typ. max. unit db khz mv mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p mv 0 -p k v (7) dpgamp characteristics (ta = ?0 to +75 c , v dd = ampv dd = 5.0v, vss = ampv ss = 0v, vrefout reference) f dc ?3db dfg = open comparator level = 600mv 0 -p comparator level = 400mv 0 -p comparator level = 200mv 0 -p comparator level = 100mv 0 -p comparator level = ?00mv 0 -p comparator level = ?00mv 0 -p comparator level = ?00mv 0 -p comparator level = ?00mv 0 -p comparator level = 600mv 0 -p, 200mv 0 -p comparator level = 400mv 0 -p, 100mv 0 -p comparator level = ?00mv 0 -p, ?00mv 0 -p comparator level = ?00mv 0 -p, ?00mv 0 -p comparator level = 600mv 0 -p, 200mv 0 -p comparator level = 400mv 0 -p, 100mv 0 -p comparator level = ?00mv 0 -p, ?00mv 0 -p comparator level = ?00mv 0 -p, ?00mv 0 -p charge switch off dpg = +0.2v charge switch on dpg = +0.5v a vdpg f cdpg v osdpg v cdpg v sdpg v nsdpg r indpg r cdpg v pkdpg dpg 11.1 30.0 ?5 570 370 175 72 ?72 ?68 ?74 ?1 113 70 ?20 ?0 24.0 12.0 55.0 0 605 400 200 100 ?05 ?00 ?00 ?00 150 100 ?55 ?09 142 90 ?50 ?03 44.5 450 13.2 85.0 +35 640 432 220 125 ?43 ?38 ?23 ?24 180 120 ?85 ?30 860 2.4 * 1) when the signal is input with the ac coupling capacitor (47 f) connected to dpg pin. * 2) the result after measuring the output waveform of amplifier internal low-pass filter or voltage value.
? 29 CXP88732/88740/88748 output resistance output current * 1 item symbol pins conditions min. typ. max. unit ma ma ma ma ma ma ma ma ma (8) ctl write circuit characteristics (ta = ?0 to +75 c , v dd = ampv dd = 5.0v, vss = ampv ss = 0v reference) reccap = ampv dd ?0.5v reccap = ampv dd + 0.5v write current = 2.0ma write current = 2.5ma write current = 3.0ma write current = 3.5ma write current = 4.0ma write current = 4.5ma write current = 5.0ma write current = 5.5ma write current = 6.0ma r oh r ol i orec reccap recctl (+) recctl ( ) 450 410 1.3 1.7 2.1 2.6 2.9 3.3 3.7 4.0 4.4 625 555 2.0 2.5 3.1 3.6 4.0 4.6 5.1 5.6 6.1 1005 840 2.9 3.7 4.5 5.2 5.9 6.6 7.2 8.0 8.9 * 1) the current value which flows when recctl (+) pin and recctl (? pin are shorted. amplifier operating current i amp ampv dd item symbol pins conditions min. typ. max. unit ma a (9) amplifier operating current characteristics (ta = ?0 to +75 c , v dd = ampv dd = 5.0v, vss = ampv ss = 0v reference) 12.0 10 when the amplifier is operating * 1 when the amplifier is not operating 7.6 * 1) the ctl recording current is added during ctl write. note) the amplifier operation and not-operation is controlled according to the contents of amplifier power supply control register (aswc: 05e2 h ) bits 5, 4, 1 and 0.
? 30 CXP88732/88740/88748 supplement fig. 9. recommended oscillation circuit a a a a a a a a a a a a e x t a l x t a l c 1 c 2 r d ( i ) a a a a a a a a a a a a t e x t x c 1 c 2 r d ( i i ) manufacturer river eletec co., ltd. kinseki ltd. model hc-49/u03 hc-49/u (-s) p3 fc (mhz) 8.00 10.00 12.00 8.00 10.00 16.00 12 12 10 5 16 (12) 16 (12) 10 16.00 5 16 (12) 16 (12) 0 0 c 1 (pf) c 2 (pf) rd ( ) circuit example (i) (i) 470k (ii) mask option table 12.00 12 12 32.768khz 18 30 * 1) the input circuit format can be selected for pe3/sync pin. item content reset pin pull-up resistor input circuit format * 1 non-existent cmos schmitt existent ttl schmitt
? 31 CXP88732/88740/88748 3 4 5 6 1 1 0 0 i d d v s . v d d ( f c = 1 6 m h z , t a = 2 5 c , t y p i c a l ) i d d s u p p l y c u r r e n t [ m a ] 1 0 v d d s u p p l y v o l t a g e [ v ] 3 2 k h z s l e e p m o d e i d d v s . f c ( v d d = 5 . 0 v , t a = 2 5 c , t y p i c a l ) 5 1 0 1 5 0 5 1 0 1 5 2 0 2 5 f c s y s t e m c l o c k [ m h z ] 3 0 0 . 1 0 . 0 1 s l e e p m o d e 1 / 1 6 d i v i d i n g m o d e 1 / 2 d i v i d i n g m o d e 2 0 1 / 2 d i v i d i n g m o d e 1 / 4 d i v i d i n g m o d e 1 / 1 6 d i v i d i n g m o d e s l e e p m o d e 1 / 4 d i v i d i n g m o d e 3 2 k h z m o d e i d d s u p p l y c u r r e n t [ m a ] 1 6 3 5 2 characteristics curve
? 32 CXP88732/88740/88748 package outline unit: mm s o n y c o d e e i a j c o d e j e d e c c o d e p a c k a g e m a t e r i a l l e a d t r e a t m e n t l e a d m a t e r i a l p a c k a g e m a s s e p o x y r e s i n s o l d e r p l a t i n g 4 2 / c o p p e r a l l o y p a c k a g e s t r u c t u r e 2 3 . 9 0 . 4 q f p - 1 0 0 p - l 0 1 1 0 0 p i n q f p ( p l a s t i c ) 2 0 . 0 0 . 1 + 0 . 4 0 . 1 5 0 . 0 5 + 0 . 1 1 5 . 8 0 . 4 1 7 . 9 0 . 4 1 4 . 0 0 . 1 + 0 . 4 2 . 7 5 0 . 1 5 + 0 . 3 5 a 0 . 6 5 m 0 . 1 3 q f p 1 0 0 - p - 1 4 2 0 1 . 7 g 1 1 0 0 8 1 8 0 5 1 5 0 3 1 3 0 0 . 3 0 . 1 + 0 . 1 5 d e t a i l a 0 t o 1 0 0 . 8 0 . 2 ( 1 6 . 3 ) 0 . 1 5 0 . 1 0 . 0 5 + 0 . 2

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